Multi-phase clock systems are known, especially in time-interleaved applications. Time-interleaving is a technique which finds wide application in circuit design, for example, in Analog-to-Digital Converters (ADC's) and clock and data recovery (CDR) circuits. This technique entails the use of several parallel data processing paths, each with limited speed.
In essence, interleaving means that chip area is spent in return for speed of operation. Where accurate and fast operation is required, interleaving allows the combination of accurate but slow paths into a system that becomes both accurate and fast. In interleaved systems, a multi-phase clock is required. The accuracy of the system is limited by the time accuracy of the multi-phase clock. In particular, differences between the actual and ideal timing of a clock edge (skew) is a limiting factor. Skew may be caused by mismatch in the multi-phase oscillator, but it may also be caused by layout asymmetry, since it is non-trivial to generate a perfectly symmetrical layout with identical delays for all paths in an interleaved system.
To generate a multi-phase clock, a high frequency clock can be divided down to a lower frequency clock with many phases. Although the phase accuracy of this method is acceptable, it is a “power-hungry” approach, requiring many high-speed dividers and retiming flip-flops. Moreover, at very high frequencies, it may not be possible to generate the required HF signal at all. An alternative approach for producing a multiphase clock is to make a multi-phase ring oscillator. This is advantageous because the interval between two active clock edges may be very small (the propagation delay of a gate). However, this approach is limited by the accuracy by which a large number of phases can be produced, since some timing errors in the ring will accumulate.
There are many different ways in which the skew in an interleaved system can be measured and removed by calibration. In interleaved ADC's, skew is sometimes measured by spectral analysis of the digital output when the input is known. There are other methods of measuring and calibrating skew known in the prior art.
A multi-phase clock system having skew measurement and calibration is disclosed in L. Wu and J. William C. Black. “A low-jitter skew-calibrated multi-phase clock generator for time-interleaved applications”, Proceedings of the ISSCC, 2001, page 25.3. This document discloses a multiphase clock generator comprising a 4-stage differential ring-oscillator which produces 8 different clock phases at its output. Each output is provided with an additional delay adjustment unit. The output of only one of the delay adjustment units is coupled back into a phase detector which compares this output signal with a reference clock. The phase detector steers a chargepump, which drives the loop filter, which drives the ring oscillator, thus effectively closing the loop of a phase-locked loop. Coarse tuning of the ring-oscillator is done by the output signal of the loop filter which is used as a global control voltage for all stages of the ring-oscillator. Fine tuning of individual clock phases is done by means of individual control voltages, which are produced by delay comparators, wherein the delay comparators are arranged for comparing time intervals between selected subsets of the individual clock phases in order to regulate the actual time events towards the desired time events. The fifth phase of the multi-phase clock is de-skewed by comparing a first time interval between the first phase and the fifth phase with a second time interval between the fifth phase and the first phase of the next clock cycle; if the first interval is longer than the second interval, the delay of the additional delay adjustment unit is increased, and visa versa. The third phase is similarly de-skewed by comparing a third time interval between the first phase and the third phase with a fourth time interval between the third phase and the fifth phase, whereafter the delay adjustment unit of the third clock phase is adjusted accordingly. For the seventh phase, the time interval between the fifth phase and the seventh phase is compared with the time interval between the seventh phase and the first phase of the next clock period. De-skewing of the second, fourth, and sixth clock phase happens in a manner similar to that described above.
A disadvantage of the known multi-phase clock system is that it is not suitable for high frequencies. The circuit's operation relies on continuously measuring short time intervals between the individual clock phases within a single clock period and continuously comparing them to generate the appropriate references for the same clock phases. The measurement of time intervals between the individual clock phases becomes increasingly difficult at higher frequencies and also becomes relatively less accurate. As a consequence, the known circuit has a maximum operational clock frequency that is limited by the accuracy of the time interval measurement.